ST STM32F405

General-purpose timers (TIM2 to TIM5) RM0090
600/1749 RM0090 Rev 18
Figure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 151. Counter timing diagram, internal clock divided by N
MS37344V1
0034 0035
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow (cnt_ovf)
Update interrupt flag (UIF)
CNT_EN
0036 0035
MS37345V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Update interrupt flag (UIF)
Counter underflow
001F20 01