ST STM32F405

Flexible memory controller (FMC) RM0090
1620/1749 RM0090 Rev 18
Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 460. ModeA read access waveforms
1. NBL[3:0] are driven low during the read access
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 0.
Table 270. FMC_BTRx bit fields (continued)
Bit
number
Bit name Value to set
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[31:0]
HCLK cycles HCLK cycles
NWE
NBL[3:0]
data driven
by memory
MS30454V1
High