ST STM32F405 User Manual

Interrupts and events RM0090
380/1749 RM0090 Rev 18
12.2.2 EXTI block diagram
Figure 41 shows the block diagram.
Figure 41. External interrupt/event controller block diagram
12.2.3 Wakeup event management
The STM32F4xx are able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex
®
-M4 with FPU System Control register. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
• or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
To use an external line as a wakeup event, refer to Section 12.2.4: Functional description.
12.2.4 Functional description
To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
Peripheral interface
Edge detect
circuit
AMBA APB bus
PCLK2
23
23 23
2323
23
23
To NVIC interrupt
controller
Software
interrupt
event
register
Rising
trigger
selection
register
23
Event
mask
register
Pulse
generator
23
23
23
23
Input
line
Pending
request
register
23
MS32662V1
Interrupt
mask
register
Falling
trigger
selection
register

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English