ST STM32F405 User Manual

RM0090 Rev 18 73/1749
RM0090 Embedded Flash memory interface
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3 Embedded Flash memory interface
3.1 Introduction
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2 Main features
• Flash memory read operations
• Flash memory program/erase operations
• Read / write protections
• Prefetch on I-Code
• 64 cache lines of 128 bits on I-Code
• 8 cache lines of 128 bits on D-Code
Figure 3 shows the Flash memory interface connection inside the system architecture.
Figure 3. Flash memory interface connection inside system architecture
(STM32F405xx/07xx and STM32F415xx/17xx)
Cortex
core
Ethernet
USB HS
DMA1
DMA2
D-code bus
I-Code bus
Cortex-M4 with FPU
I-Code
D-Code
S bus
AHB
periph1
Flash
memory
Flash interface
SRAM and
External
memories
AHB
periph2
FLITF registers
AHB
32-bit
instruction
bus
Access to instruction in Flash memory
Access to data and literal pool in Flash memory
FLITF register access
MS30468V3
CCM data
RAM
AHB
32-bit
data bus
AHB
32-bit
system bus
Flash
memory
bus
128 bits

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English