ST STM32F405 User Manual

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1132/1749 RM0090 Rev 18
The RMII is instantiated between the MAC and the PHY. This helps translation of the MAC’s
MII into the RMII. The RMII block has the following characteristics:
• It supports 10-Mbit/s and 100-Mbit/s operating rates
• The clock reference must be doubled to 50 MHz
• The same clock reference must be sourced externally to both MAC and external
Ethernet PHY
• It provides independent 2-bit wide (dibit) transmit and receive data paths
Figure 356. Reduced media-independent interface signals
RMII clock sources
Either clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to
generate the 50 MHz frequency.
Figure 357. RMII clock sources
33.4.4 MII/RMII selection
The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
SYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
STM32
MCU
TXD[1:0]
TX_EN
RXD[1:0]
CRS_DV
MDC
MDIO
REF_ CLK
Clock source
802.3 MAC
External
PHY
ai15624b
MS19930V1
STM32
MCU
REF_CLK
50 MHz
25 MHz
PLL
For 10/100 Mbit/s
External
PHY
802.3 MAC

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English