Controller area network (bxCAN) RM0090
1088/1749 RM0090 Rev 18
Filter bank scale and mode configuration
The filter banks are configured by means of the corresponding CAN_FMR register. To
configure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR
register. The filter scale is configured by means of the corresponding FSCx bit in the
CAN_FS1R register, refer to Figure 342. The identifier list or identifier mask mode for the
corresponding Mask/Identifier registers is configured by means of the FBMx bits in the
CAN_FMR register.
To filter a group of identifiers, configure the Mask/Identifier registers in mask mode.
To select single identifiers, configure the Mask/Identifier registers in identifier list mode.
Filters not used by the application should be left deactivated.
Each filter within a filter bank is numbered (called the Filter Number) from 0 to a maximum
dependent on the mode and the scale of each of the filter banks.
Concerning the filter configuration, refer to Figure 342.
Figure 342. Filter bank scale configuration - register organization
Filter match index
Once a message has been received in the FIFO it is available to the application. Typically,
application data is copied into SRAM locations. To copy the data to the right location the
One 32-Bit Filter - Identifier Mask
Two 16-Bit Filters - Identifier Mask
CAN_FxR1[31:24]
CAN_FxR2[31:24]
CAN_FxR1[15:8]
CAN_FxR1[31:24]
CAN_FxR1[7:0]
CAN_FxR1[23:16]
x = filter bank number
FSCx = 1FSCx = 0
1
These bits are located in the CAN_FS1R register
Filter Bank Scale
ID
Mask
ID
Mask
STID[10:3]
STID[2:0]
EXID[12:5]
Mapping
STID[10:3]
ID
Mask
Mapping
RTR
Two 32-Bit Filters - Identifier List
ID
ID
STID[10:3] STID[2:0] EXID[12:5]
Mapping
Four 16-Bit Filters - Identifier List
ID
ID
STID[10:3]
ID
ID
Mapping
n
n+1
n+2
n+3
n+1
Filter Bank Mode
2
n
n
n+1
EXID[4:0] IDE
EXID[17:13]
EXID[17:13]
STID[2:0] RTR IDE EXID[17:15]
FBMx = 0FBMx = 1
Filter
2
These bits are located in the CAN_FM1R register
n
Num.
FBMx = 0FBMx = 1
Config. Bits
1
STID[2:0] RTR IDE EXID[17:15]
0
RTREXID[4:0] IDE 0
CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0]
CAN_FxR2[7:0]CAN_FxR2[15:8]CAN_FxR2[23:16]
CAN_FxR1[31:24]
CAN_FxR2[31:24]
CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0]
CAN_FxR2[7:0]CAN_FxR2[15:8]CAN_FxR2[23:16]
CAN_FxR2[15:8]
CAN_FxR2[31:24]
CAN_FxR2[7:0]
CAN_FxR2[23:16]
CAN_FxR1[15:8]
CAN_FxR1[31:24]
CAN_FxR1[7:0]
CAN_FxR1[23:16]
CAN_FxR2[15:8]
CAN_FxR2[31:24]
CAN_FxR2[7:0]
CAN_FxR2[23:16]
ID=Identifier
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