ST STM32F405 User Manual

Flexible memory controller (FMC) RM0090
1650/1749 RM0090 Rev 18
37.6.2 NAND Flash / PC Card supported memories and transactions
Table 293 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND Flash / PC Card controller are shown in gray.
37.6.3 Timing diagrams for NAND Flash memory and PC Card
Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of
registers:
• Control register: FMC_PCRx
• Interrupt status register: FMC_SRx
• ECC register: FMC_ECCRx
• Timing register for Common memory space: FMC_PMEMx
• Timing register for Attribute memory space: FMC_PATTx
• Timing register for I/O space: FMC_PIOx
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,
plus one parameter that defines the timing for starting driving the data bus when a write
access is performed. Figure 476 shows the timing parameter definitions for common
memory accesses, knowing that Attribute and I/O (only for PC Card) memory space access
timings are similar.
Table 293. Supported memories and transactions
Device Mode R/W
AHB
data size
Memory
data size
Allowed/
not allowed
Comments
NAND 8-bit
Asynchronous R 8 8 Y -
Asynchronous W 8 8 Y -
Asynchronous R 16 8 Y Split into 2 FMC accesses
Asynchronous W 16 8 Y Split into 2 FMC accesses
Asynchronous R 32 8 Y Split into 4 FMC accesses
Asynchronous W 32 8 Y Split into 4 FMC accesses
NAND 16-bit
Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
Asynchronous R 32 16 Y Split into 2 FMC accesses
Asynchronous W 32 16 Y Split into 2 FMC accesses

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English