ST STM32F405 User Manual

USB on-the-go full-speed (OTG_FS) RM0090
1258/1749 RM0090 Rev 18
Figure 391. Updating OTG_FS_HFIR dynamically
34.10 USB data FIFOs
The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control
mechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space
into Tx-FIFOs into which the application pushes the data to be temporarily stored before the
USB transmission, and into a single Rx FIFO where the data received from the USB are
temporarily stored before retrieval (popped) by the application. The number of instructed
FIFOs and how these are organized inside the RAM depends on the device’s role. In
peripheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO
size is software configured to better meet the application requirements.
400
…
…
……
450
Latency
SOF
reload
OTG_FS_HFIR
write
value
Frame
timer
Old OTG_FS_HIFR value
= 400 periods
OTG_FS_HIFR value
= 450 periods+HIFR write latency
New OTG_FS_HIFR value
= 450 periods
1
400
0
399
1
400
0
399 450 449
1
450
0
449
1
450
0
449
OTG_FS_HFIR
ai18
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ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English