ST STM32F405 User Manual

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
1126/1749 RM0090 Rev 18
33.4 Ethernet functional description: SMI, MII and RMII
The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated
DMA controller. It supports both default media-independent interface (MII) and reduced
media-independent interface (RMII) through one selection bit (refer to SYSCFG_PMC
register).
The DMA controller interfaces with the Core and memories through the AHB Master and
Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave
interface accesses Control and Status Registers (CSR) space.
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before
transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet
frames received from the line until they are transferred to system memory by the DMA.
The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of
configuration registers permit the user to select the desired mode and features for the MAC
and the DMA controller.
Note: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Figure 350. ETH block diagram
1. For AHB connections refer to Figure 1: System architecture for STM32F405xx/07xx and
STM32F415xx/17xx devices and Figure 2: System architecture for STM32F42xxx and STM32F43xxx
devices.
33.4.1 Station management interface: SMI
The station management interface (SMI) allows the application to access any PHY registers
through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.
The application can select one of the 32 PHYs and one of the 32 registers within any PHY
and send control data or receive status information. Only one register in one PHY can be
addressed at any given time.
Both the MDC clock line and the MDIO data line are implemented as alternate function I/O
in the microcontroller:
• MDC: a periodic clock that provides the timing reference for the data transfer at the
maximum frequency of 2.5 MHz. The minimum high and low times for MDC must be
2 Kbyte
RX FIFO
Ethernet
DMA
Media access
control
MAC 802.3
MAC
control
registers
DMA
control &
status
registers
Operation
mode
register
Interface
Select
MII
MDC
MDIO
AHB Slave interface
RMII
ai15620c
Bus matrix
External PHY
Checksum
offload
PTP
IEEE1588
PMT MMC
2 Kbyte
TX FIFO

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English