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ST STM32F405 User Manual

ST STM32F405
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Universal synchronous asynchronous receiver transmitter (USART) RM0090
1004/1749 RM0090 Rev 18
RTS flow control
If the RTS flow control is enabled (RTSE=1), then RTS is asserted (tied low) as long as the
USART receiver is ready to receive a new data. When the receive register is full, RTS is
deasserted, indicating that the transmission is expected to stop at the end of the current
frame. Figure 318 shows an example of communication with RTS flow control enabled.
Figure 318. RTS flow control
CTS flow control
If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input
before transmitting the next frame. If CTS is asserted (tied low), then the next data is
transmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. When CTS is deasserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure
below shows an example of communication with CTS flow control enabled.
MSv31168V2
Start
bit
Start
bit
Stop
bit
Idle
Stop
bit
RX
RTS
Data 1 read
Data 2 can now be transmitted
RXNE
RXNE
Data 1 Data 2

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ST STM32F405 Specifications

General IconGeneral
BrandST
ModelSTM32F405
CategoryComputer Hardware
LanguageEnglish

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