Flexible memory controller (FMC) RM0090
1618/1749 RM0090 Rev 18
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FMC _BCRx, and FMC_BTRx/FMC_BWTRx registers.
Figure 458. Mode1 read access waveforms
Figure 459. Mode1 write access waveforms
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[31:0]
HCLK cycles HCLK cycles
NWE
NBL[3:0]
data driven
by memory
MS30452V1
High
A[25:0]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
D[31:0]
HCLK cycles HCLK cycles
NWE
NBL[3:0]
data driven by FSMC
MS30453V1
1HCLK
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