RM0090 Rev 18 189/1749
RM0090 Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
212
6.3.15 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x7EEF 97FF
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.
OTGHS
ULPILPE
N
OTGH
S
LPEN
ETHPT
P
LPEN
ETHRX
LPEN
ETHTX
LPEN
ETHMA
C
LPEN
Res.
DMA2D
LPEN
DMA2
LPEN
DMA1
LPEN
Res.
SRAM3
LPEN
BKPSRA
M
LPEN
SRAM
2
LPEN
SRAM
1
LPEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITF
LPEN
Reserved
CRC
LPEN
Res.
GPIOK
LPEN
GPIOIJ
LPEN
GPIOI
LPEN
GPIOH
LPEN
GPIOG
G
LPEN
GPIO
F
LPEN
GPIOE
LPEN
GPIOD
LPEN
GPIOC
LPEN
GPIOB
LPEN
GPIOA
LPEN
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode
This bit is set and cleared by software. It must be cleared when the OTG_HS is used in FS
mode.
0: USB OTG HS ULPI clock disabled during Sleep mode
1: USB OTG HS ULPI clock enabled during Sleep mode
Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode
This bit is set and cleared by software.
0: USB OTG HS clock disabled during Sleep mode
1: USB OTG HS clock enabled during Sleep mode
Bit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet PTP clock disabled during Sleep mode
1: Ethernet PTP clock enabled during Sleep mode
Bit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet reception clock disabled during Sleep mode
1: Ethernet reception clock enabled during Sleep mode
Bit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet transmission clock disabled during sleep mode
1: Ethernet transmission clock enabled during sleep mode
Bit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet MAC clock disabled during Sleep mode
1: Ethernet MAC clock enabled during Sleep mode
Bit 24 Reserved, must be kept at reset value.
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