ST STM32F405 - Figure 139. Counter Timing Diagram, Internal Clock Divided by 4; Figure 140. Counter Timing Diagram, Internal Clock Divided by N

General-purpose timers (TIM2 to TIM5) RM0090
594/1749 RM0090 Rev 18
Figure 139. Counter timing diagram, internal clock divided by 4
Figure 140. Counter timing diagram, internal clock divided by N
0000 00010035 0036
MSv37301V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
CNT_EN
MSv37302V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
001F 20