Flexible static memory controller (FSMC) RM0090
1556/1749 RM0090 Rev 18
Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 438. ModeA read accesses
1. NBL[1:0] are driven low during read access.
1 MUXE 0x0
0 MBKEN 0x1
Table 227. FSMC_BTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD Don’t care
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST HCLK cycles for read accesses).
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 0.
Table 226. FSMC_BCRx bit fields (continued)
Bit number Bit name Value to set
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven
by memory
ai15559
High
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