EasyManuals Logo

ST STM32F405 User Manual

ST STM32F405
1749 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #1269 background imageLoading...
Page #1269 background image
RM0090 Rev 18 1269/1749
RM0090 USB on-the-go full-speed (OTG_FS)
1380
Data FIFO (DFIFO) access register map
These registers, available in both host and device modes, are used to read or write the FIFO
space for a specific endpoint or a channel, in a given direction. If a host channel is of type
IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type OUT, the
FIFO can only be written on the channel.
OTG_FS_DIEPCTLx
0x920
0x940
0x960
OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3,
where x = Endpoint_number) on page 1311
OTG_FS_DIEPINTx 0x908
OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx)
(x = 0..3, where x = Endpoint_number) on page 1318
OTG_FS_DIEPTSIZ0 0x910
OTG_FS device IN endpoint 0 transfer size register
(OTG_FS_DIEPTSIZ0) on page 1320
OTG_FS_DTXFSTSx 0x918
OTG_FS device IN endpoint transmit FIFO status register
(OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) on
page 1324
OTG_FS_DIEPTSIZx
0x930
0x950
0x970
OTG_FS device OUT endpoint-x transfer size register
(OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) on
page 1324
OTG_FS_DOEPCTL0 0xB00
OTG_FS device control OUT endpoint 0 control register
(OTG_FS_DOEPCTL0) on page 1314
OTG_FS_DOEPCTLx
0xB20
0xB40
0xB60
OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3,
where x = Endpoint_number) on page 1311
OTG_FS_DOEPINTx 0xB08
OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx)
(x = 0..3, where x = Endpoint_number) on page 1319
OTG_FS_DOEPTSIZ0 0xB10
OTG_FS device OUT endpoint 0 transfer size register
(OTG_FS_DOEPTSIZ0) on page 1322
OTG_FS_DOEPTSIZx
0xB30
0xB50
0xB70
OTG_FS device OUT endpoint-x transfer size register
(OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) on
page 1324
Table 200. Device-mode control and status registers (continued)
Acronym
Offset
address
Register name
Table 201. Data FIFO (DFIFO) access register map
FIFO access register section Address range Access
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
0x1000–0x1FFC
w
r
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
0x2000–0x2FFC
w
r

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F405 and is the answer not in the manual?

ST STM32F405 Specifications

General IconGeneral
BrandST
ModelSTM32F405
CategoryComputer Hardware
LanguageEnglish

Related product manuals