ST STM32F405

RM0090 Rev 18 1669/1749
RM0090 Flexible memory controller (FMC)
1682
Figure 481. Read access crossing row boundary
Figure 482. Write access crossing row boundary
MS30446V2
Data[31:0]
NCAS
NRA S
A[12:0]
SDCLK
Col a
Col a
Col bRow n +1
Dna Dn+1 a
SDNE
TRP = 3 CAS latency = 2
NW E
Prech arge
Activate Row
Read Command
Row n
TRCD = 3
MS30447V2
Data[31:0]
NCAS
NRA S
A[12:0]
SDCLK
Cna ColaRow n+1
Dna
Dn+1a
SDNE
TRP = 3
NW E
Prech arge
Activate Row
Write command
Colb Colb
Dnb
Dn+1b
TRCD = 3