RM0090 Rev 18 1639/1749
RM0090 Flexible memory controller (FMC)
1682
11 WAITCFG 0x0
10 WRAPMOD 0x0
9 WAITPOL to be set according to memory
8 BURSTEN no effect on synchronous write
7 Reserved 0x1
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP[1:0] 0x1
1 MUXEN As needed
0 MBKEN 0x1
Table 288. FMC_BTRx bit fields
Bit No. Bit name Value to set
31-30 Reserved 0x0
29:28 ACCMOD 0x0
27-24 DATLAT Data latency
23-20 CLKDIV
0x0 to get CLK = HCLK (not supported)
0x1 to get CLK = 2 × HCLK
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0] Don’t care
Table 287. FMC_BCRx bit fields (continued)
Bit No. Bit name Value to set
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