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RM0090 Rev 18 827/1749

RM0090 Real-time clock (RTC)

838

Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization

mode.

This register is write protected. The write access procedure is described in RTC register

write protection on page 803.

26.6.10 RTC write protection register (RTC_WPR)

Address offset: 0x24

Backup domain reset value: 0x0000 0000

26.6.11 RTC sub second register (RTC_SSR)

Address offset: 0x28

Backup domain reset value: 0x0000 0000

System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

1514131211109876543210

Reserved

KEY

wwwwwwww

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY: Write protection key

This byte is written by software.

Reading this byte always returns 0x00.

Refer to RTC register write protection for a description of how to unlock RTC register write

protection.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

rrrrrrrrrrrrrrrr

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SS[15:0]

rrrr rrrrrrrrrr r r

Bits 31:16 Reserved

Bits 15:0 SS: Sub second value

SS[15:0] is the value in the synchronous prescaler’s counter. The fraction of a second is

given by the formula below:

Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 )

Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct

time/date is one second less than as indicated by RTC_TR/RTC_DR.

ST STM32F405 User Manual

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