ST STM32F405 User Manual

RM0090 Rev 18 1743/1749
RM0090 Revision history
1743
07-Jun-2018 17
Updated:
– Figure 16: Clock tree (STM32F42xxx an STM32F43xxx) and Figure 21: Clock
tree (STM32F405xx/07xx and STM32F415xx/17xx)
– Figure 27: Selecting an alternate function on STM32F42xxx and STM32F43xxx
– Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx and
Table 62: Vector table for STM32F42xxx and STM32F43xxx
– Section 29.17.5: SAI xInterrupt mask register (SAI_xIM) where x is A or B
– Section 38.6.1: MCU device ID code
25-Feb-2019 18
Section 6: Reset and clock control for STM32F42xxx and STM32F43xxx
(RCC)
Updated OTGHSULPILPEN bit description in RCC AHB1 peripheral clock enable in
low power mode register (RCC_AHB1LPENR) and OTGHSULPIEN bit description
in RCC AHB1 peripheral clock register (RCC_AHB1ENR).
Section 7: Reset and clock control for STM32F405xx/07xx and
STM32F415xx/17xx(RCC):
Updated RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) reset value.
Updated OTGHSULPILPEN bit description in RCC AHB1 peripheral clock enable in
low power mode register (RCC_AHB1LPENR) and OTGHSULPIEN bit description
in RCC AHB1 peripheral clock enable register (RCC_AHB1ENR).
Section 13: Analog-to-digital converter (ADC)
Update Section : Dual ADC mode.
Section 17: Advanced-control timers (TIM1 and TIM8)
Updated Figure 113: Capture/compare channel 1 main circuit.
Figure 19: General-purpose timers (TIM9 to TIM14)
Updated Figure 194: Capture/compare channel 1 main circuit.
Section 34: USB on-the-go full-speed (OTG_FS)
Updated Section : SETUP and OUT data transfers and Updated Section : IN data
transfers. Modified Table 200: Device-mode control and status registers.
Section 35: USB on-the-go high-speed (OTG_HS)
Updated Table 208: Core global control and status registers (CSRs) and Table 210:
Device-mode control and status registers.
Updated Section : OTG_HS device IN endpoint transmit FIFO size register
(OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number), Section : OTG
device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x =
Endpoint_number), Section : OTG_HS device endpoint-x control register
(OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number), Section : OTG_HS
device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where
x = Endpoint_number), Section : OTG_HS device endpoint-x interrupt register
(OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number), Section : OTG_HS
device endpoint-x DMA address register (OTG_HS_DIEPDMAx /
OTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number).
Updated Section : SETUP and OUT data transfers and Section : IN data transfers
.
Se
ction 38: Debug support (DBG)
Updated REV_ID in DBGMCU_CR register.
Table 315. Document revision history (continued)
Date Version Changes

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English