USB on-the-go high-speed (OTG_HS) RM0090
1430/1749 RM0090 Rev 18
OTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx)
(x = 1..5, where x is the FIFO_number)
Address offset: 0x104 + 0x04 * (x - 1)
Reset value: 0x02000400
35.12.3 Host-mode registers
Bit values in the register descriptions are expressed in binary unless otherwise specified.
Host-mode registers affect the operation of the core in the host mode. Host mode registers
must not be accessed in peripheral mode, as the results are undefined. Host mode registers
can be categorized as follows:
OTG_HS host configuration register (OTG_HS_HCFG)
Address offset: 0x400
Reset value: 0x0000 0000
This register configures the core after power-on. Do not change to this register after
initializing the host.
313029282726252423222120191817161514131211109876543210
PTXFD PTXSA
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:16 PTXFD: Host periodic TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 512
Bits 15:0 PTXSA: Host periodic TxFIFO start address
The power-on reset value of this register is the sum of the largest Rx data FIFO depth and
largest nonperiodic Tx data FIFO depth.
313029282726252423222120191817161514131211109876543210
INEPTXFD INEPTXSA
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 512
The power-on reset value of this register is specified as the largest IN endpoint FIFO
number depth.
Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address
This field contains the memory start address for IN endpoint transmit FIFOx. The address
must be aligned with a 32-bit memory location.
To Next Page
Loading...
Need help?
General
