RM0090 Rev 18 1741/1749
RM0090 Revision history
1743
20-Sep-2016 13
Analog-to-digital converter (ADC)
Updated DMA mode 1 and DMA mode 3 description in Section 13.9: Multi ADC
mode.
LCD-TFT controller
Updated values to be programmed to LTDC_SSCR in Section : Example of
Synchronous timings configuration
Updated Section 16.4.2: Layer programmable parameters/Windowing.
Advanced-control timers (TIM1 and TIM8)
Updated Section 17.3.21: Debug mode.
Extended Section 17.4.20: TIM1 and TIM8 DMA address for full transfer
(TIMx_DMAR) to 32 bits.
Updated Table 95: Output control bits for complementary OCx and OCxN channels
with break feature output state for MOE = 0.
Updated TIM1 and TIM8 auto-reload register (TIMx_ARR) reset value.
Updated TIMx_CCR1/2/3/4 description when CC1 channel is configured as inputs
and changed bit access type to rw/ro.
General-purpose timers (TIM2 to TIM5)
Updated TIMx auto-reload register (TIMx_ARR) reset value.
Updated TIMx_CCR1/2/3/4 description when CC1 channel is configured as inputs
and changed bit access type to rw/ro.
General-purpose timers (TIM9 to TIM14)
Updated TIM9/12 auto-reload register (TIMx_ARR) and TIM10/11/13/14 auto-
reload register (TIMx_ARR) reset value.
Updated TIMx_CCR1 description when CC1 channel is configured as inputs and
changed bit access type to rw/ro.
Basic timers (TIM6 to TIM7)
Updated TIM6 and TIM7 auto-reload register (TIMx_ARR).
Secure digital input/output interface (SDIO)
Updated Section 31.1: SDIO main features up to 50 MHz.
Updated Section 31.3: SDIO functional description SDIO_CK description.
Updated note removing 48 MHz in Section 31.9.1: SDIO power control register
(SDIO_POWER), Section 31.9.2: SDI clock control register (SDIO_CLKCR),
Section 31.9.4: SDIO command register (SDIO_CMD) and Section 31.9.9: SDIO
data control register (SDIO_DCTRL).
Table 315. Document revision history (continued)
Date Version Changes
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