ST STM32F405 User Manual

General-purpose timers (TIM2 to TIM5) RM0090
642/1749 RM0090 Rev 18
Note: The state of the external IO pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.
18.4.10 TIMx counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
18.4.11 TIMx prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
18.4.12 TIMx auto-reload register (TIMx_ARR)
Address offset: 0x2C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT[31:16] (depending on timers)
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CNT[15:0]
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Bits 31:16 CNT[31:16]: High counter value (on TIM2 and TIM5).
Bits 15:0 CNT[15:0]: Counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
Reset value: 0xFFFF FFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR[31:16] (depending on timers)
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ARR[15:0]
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ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English