ST STM32F405

General-purpose timers (TIM9 to TIM14) RM0090
692/1749 RM0090 Rev 18
19.5.7 TIM10/11/13/14 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
19.5.8 TIM10/11/13/14 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
19.5.9 TIM10/11/13/14 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
1514131211109876543210
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 CNT[15:0]: Counter value
1514131211109876543210
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
1514131211109876543210
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 19.3.1: Time-base unit for more details about ARR update and behavior.
The counter is blocked while the auto-reload value is null.