Revision history RM0090
1740/1749 RM0090 Rev 18
17-May-2016
12
(continued)
General-purpose timers (TIM6 and TIM7)
Updated Section 20.4.7: TIM6 and TIM7 prescaler (TIMx_PSC).
Real-time clock (RTC)
Updated conditions for running under System reset in Section 26.3.7: Resetting the
RTC.
Updated Section 26.3.14: Calibration clock output.
Added note related to TSE in Section 26.6.3: RTC control register (RTC_CR).
Updated caution note related to TAMP1TRG in Section 26.6.17: RTC tamper and
alternate function configuration register (RTC_TAFCR) register.
Universal synchronous asynchronous receiver transmitter (USART)
Replaced all occurrences of nCTS by CTS, nRTS by RTS and SCLK by CK.
Flexible static memory controller (FSMC)
Updated Section 36.3: AHB interface.
Added note related to the hold phase delay below Figure 454: NAND/PC Card
controller timing for common memory access.
Updated Section 36.6.5: NAND Flash prewait functionality.
Updated BUSTURN description in Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FSMC_BTR1..4).
Updated MEMHOLDx in Section : Common memory space timing register 2..4
(FSMC_PMEM2..4) and ATTHOLD in Section : Attribute memory space timing
registers 2..4 (FSMC_PATT2..4).
Flexible memory controller (FMC)
Updated Section 37.3: AHB interface.
Added note related to the hold phase delay below Figure 476: NAND Flash/PC
Card controller waveforms for common memory access.
Updated Section 37.6.5: NAND Flash prewait functionality.
Updated BUSTURN description in Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FMC_BTR1..4).
Updated MEMHOLDx in Section : Common memory space timing register 2..4
(FMC_PMEM2..4) and ATTHOLD in Section : Attribute memory space timing
registers 2..4 (FMC_PATT2..4).
Debug (DBG)
Updated value to be programmed to the
ETM Trace Start/stop register to enable
the trace in Section 38.15.4: ETM configuration example.
Table 315. Document revision history (continued)
Date Version Changes