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RM0090 Rev 18 1219/1749

RM0090 Ethernet (ETH): media access control (MAC) with DMA controller

1239

Ethernet PTP time stamp low register (ETH_PTPTSLR)

Address offset: 0x070C

Reset value: 0x0000 0000

This register contains the least significant (lower) 32 time bits. This read-only register

contains the subsecond system time value.

Ethernet PTP time stamp high update register (ETH_PTPTSHUR)

Address offset: 0x0710

Reset value: 0x0000 0000

This register contains the most significant (higher) 32 bits of the time to be written to, added

to, or subtracted from the System Time value. The Time stamp high update register, along

with the Time stamp update low register, initializes or updates the system time maintained

by the MAC. You have to write both of these registers before setting the TSSTI or TSSTU

bits in the Time stamp control register.

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STPNS

STSS

r rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr

Bit 31 STPNS: System time positive or negative sign

This bit indicates a positive or negative time value. When set, the bit indicates that time

representation is negative. When cleared, it indicates that time representation is positive.

Because the system time should always be positive, this bit is normally zero.

Bits 30:0 STSS: System time subseconds

The value in this field has the subsecond time representation, with 0.46 ns accuracy.

313029282726252423222120191817161514131211109876543210

TSUS

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 TSUS: Time stamp update second

The value in this field indicates the time, in seconds, to be initialized or added to the system

time.

ST STM32F405 User Manual

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