ST STM32F405 User Manual

RM0090 Rev 18 1295/1749
RM0090 USB on-the-go full-speed (OTG_FS)
1380
OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK)
Address offset: 0x418
Reset value: 0x0000 0000
The host all channel interrupt mask register works with the host all channel interrupt register
to interrupt the application when an event occurs on a channel. There is one interrupt mask
bit per channel, up to a maximum of 16 bits.
OTG_FS Host port control and status register (OTG_FS_HPRT)
Address offset: 0x440
Reset value: 0x0000 0000
This register is available only in host mode. Currently, the OTG host supports only one port.
A single register holds USB port-related information such as USB reset, enable, suspend,
resume, connect status, and test mode for each port. It is shown in Figure 394. The rc_w1
bits in this register can trigger an interrupt to the application through the host port interrupt
bit of the core interrupt register (HPRTINT bit in OTG_FS_GINTSTS). On a Port Interrupt,
the application must read this register and clear the bit that caused the interrupt. For the
rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
313029282726252423222120191817161514131211109876543210
Reserved
HAINTM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 HAINTM: Channel interrupt mask
0: Masked interrupt
1: Unmasked interrupt
One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
313029282726252423222120191817161514131211109876 543210
Reserved
PSPD PTCTL
PPWR
PLSTS
Reserved
PRST
PSUSP
PRES
POCCHNG
POCA
PENCHNG
PENA
PCDET
PCSTS
r r rw rw rw rw rw r r rw rs rw
rc_
w1
r
rc_
w1
rc_
w0
rc_
w1
r
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:17 PSPD: Port speed
Indicates the speed of the device attached to this port.
01: Full speed
10: Low speed
11: Reserved

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English