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ST STM32F405 User Manual

ST STM32F405
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USB on-the-go high-speed (OTG_HS) RM0090
1388/1749 RM0090 Rev 18
35.5.3 Peripheral endpoints
The OTG_HS core instantiates the following USB endpoints:
Control endpoint 0
This endpoint is bidirectional and handles control messages only.
It has a separate set of registers to handle IN and OUT transactions, as well as
dedicated control (OTG_HS_DIEPCTL0/OTG_HS_DOEPCTL0), transfer configuration
(OTG_HS_DIEPTSIZ0/OTG_HS_DIEPTSIZ0), and status-interrupt
(OTG_HS_DIEPINTx/)OTG_HS_DOEPINT0) registers. The bits available inside the
control and transfer size registers slightly differ from other endpoints.
5 IN endpoints
They can be configured to support the isochronous, bulk or interrupt transfer type.
They feature dedicated control (OTG_HS_DIEPCTLx), transfer configuration
(OTG_HS_DIEPTSIZx), and status-interrupt (OTG_HS_DIEPINTx) registers.
The Device IN endpoints common interrupt mask register (OTG_HS_DIEPMSK)
allows to enable/disable a single endpoint interrupt source on all of the
IN endpoints (EP0 included).
They support incomplete isochronous IN transfer interrupt (IISOIXFR bit in
OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous IN endpoint for which the transfer is not completed in the current
frame. This interrupt is asserted along with the end of periodic frame interrupt
(OTG_HS_GINTSTS/EOPF).
5 OUT endpoints
They can be configured to support the isochronous, bulk or interrupt transfer type.
They feature dedicated control (OTG_HS_DOEPCTLx), transfer configuration
(OTG_HS_DOEPTSIZx) and status-interrupt (OTG_HS_DOEPINTx) registers.
The Device Out endpoints common interrupt mask register
(OTG_HS_DOEPMSK) allows to enable/disable a single endpoint interrupt source
on all OUT endpoints (EP0 included).
They support incomplete isochronous OUT transfer interrupt (INCOMPISOOUT
bit in OTG_HS_GINTSTS). This interrupt is asserted when there is at least one
isochronous OUT endpoint on which the transfer is not completed in the current
frame. This interrupt is asserted along with the end of periodic frame interrupt
(OTG_HS_GINTSTS/EOPF).

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ST STM32F405 Specifications

General IconGeneral
BrandST
ModelSTM32F405
CategoryComputer Hardware
LanguageEnglish

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