ST STM32F405 User Manual

USB on-the-go high-speed (OTG_HS) RM0090
1412/1749 RM0090 Rev 18
OTG_HS USB configuration register (OTG_HS_GUSBCFG)
Address offset: 0x00C
Reset value: 0x0000 1440
This register can be used to configure the core after power-on or a changing to host mode
or peripheral mode. It contains USB and USB-PHY related configuration parameters. The
application must program this register before starting any transactions on either the AHB or
the USB. Do not make changes to this register after the initial programming.
313029282726252423222120191817161514131211109876543210
CTXPKT
FDMOD FHMOD
Reserved
ULPIIPD
PTCI
PCCI
TSDPS
ULPIEVBUSI
ULPIEVBUSD
ULPICSM
ULPIAR
ULPIFSLS
Reserved
PHYLPCS
Reserved
TRDT
HNPCAP
SRPCAP
Reserved
PHYSEL
Reserved
TOCAL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 CTXPKT: Corrupt Tx packet
This bit is for debug purposes only. Never set this bit to 1.
Note: Accessible in both peripheral and host modes.
Bit 30 FDMOD: Forced peripheral mode
Writing a 1 to this bit forces the core to peripheral mode irrespective of the OTG_HS_ID input
pin.
0: Normal mode
1: Forced peripheral mode
After setting the force bit, the application must wait at least 25 ms before the change takes
effect.
Note: Accessible in both peripheral and host modes.
Bit 29 FHMOD: Forced host mode
Writing a 1 to this bit forces the core to host mode irrespective of the OTG_HS_ID input pin.
0: Normal mode
1: Forced host mode
After setting the force bit, the application must wait at least 25 ms before the change takes
effect.
Note: Accessible in both peripheral and host modes.
Bits 28:26 Reserved, must be kept at reset value.
Bit 25 ULPIIPD: ULPI interface protect disable
This bit controls the circuitry built in the PHY to protect the ULPI interface when the link tri-
states stp and data. Any pull-up or pull-down resistors employed by this feature can be
disabled. Please refer to the ULPI specification for more details.
0: Enables the interface protection circuit
1: Disables the interface protection circuit
Bit 24 PTCI: Indicator pass through
This bit controls whether the complement output is qualified with the internal V
BUS
valid
comparator before being used in the V
BUS
state in the RX CMD. Please refer to the ULPI
specification for more details.
0: Complement Output signal is qualified with the Internal V
BUS
valid comparator
1: Complement Output signal is not qualified with the Internal V
BUS
valid comparator

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English