ST STM32F405 User Manual

RM0090 Rev 18 1415/1749
RM0090 USB on-the-go high-speed (OTG_HS)
1543
OTG_HS reset register (OTG_HS_GRSTCTL)
Address offset: 0x010
Reset value: 0x8000 0000
The application uses this register to reset various hardware features inside the core.
313029282726252423222120191817161514131211109876543210
AHBIDL
DMAREQ
Reserved
TXFNUM
TXFFLSH
RXFFLSH
Reserved
FCRST
HSRST CSRST
rr rw rs rs rs rs rs
Bit 31 AHBIDL: AHB master idle
Indicates that the AHB master state machine is in the Idle condition.
Note: Accessible in both peripheral and host modes.
Bit 30 DMAREQ: DMA request signal
This bit indicates that the DMA request is in progress. Used for debug.
Bits 29:11 Reserved, must be kept at reset value.
Bits 10:6 TXFNUM: TxFIFO number
This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not
be changed until the core clears the TxFIFO Flush bit.
00000:
– Nonperiodic TxFIFO flush in host mode
– Tx FIFO 0 flush in peripheral mode
00001:
– Periodic TxFIFO flush in host mode
– TXFIFO 1 flush in peripheral mode
00010: TXFIFO 2 flush in peripheral mode
...
00101: TXFIFO 15 flush in peripheral mode
10000: Flush all the transmit FIFOs in peripheral or host mode.
Note: Accessible in both peripheral and host modes.
Bit 5 TXFFLSH: TxFIFO flush
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the
midst of a transaction.
The application must write this bit only after checking that the core is neither writing to the
TxFIFO nor reading from the TxFIFO. Verify using these registers:
– Read: the NAK effective interrupt ensures the core is not reading from the FIFO
– Write: the AHBIDL bit in OTG_HS_GRSTCTL ensures that the core is not writing
anything to the FIFO
Note: Accessible in both peripheral and host modes.

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English