ST STM32F405 User Manual

USB on-the-go high-speed (OTG_HS) RM0090
1422/1749 RM0090 Rev 18
OTG_HS interrupt mask register (OTG_HS_GINTMSK)
Address offset: 0x018
Reset value: 0x0000 0000
This register works with the Core interrupt register to interrupt the application. When an
interrupt bit is masked, the interrupt associated with that bit is not generated. However, the
Core Interrupt (OTG_HS_GINTSTS) register bit corresponding to that interrupt is still set.
313029282726252423222120191817161514131211109876543210
WUIM
SRQIM
DISCINT
CIDSCHGM
Reserved
PTXFEM
HCIM
PRTIM
Reserved
FSUSPM
IPXFRM/IISOOXFRM
IISOIXFRM
OEPINT
IEPINT
Reserved
EOPFM
ISOODRPM
ENUMDNEM
USBRST
USBSUSPM
ESUSPM
Reserved
GONAKEFFM
GINAKEFFM
NPTXFEM
RXFLVLM
SOFM
OTGINT
MMISM
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 WUIM: Resume/remote wakeup detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and peripheral modes.
Bit 30 SRQIM: Session request/new session detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and peripheral modes.
Bit 29 DISCINT: Disconnect detected interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and peripheral modes.
Bit 28 CIDSCHGM: Connector ID status change mask
0: Masked interrupt
1: Unmasked interrupt
Note: Accessible in both host and peripheral modes.
Bit 27 Reserved, must be kept at reset value.
Bit 26 PTXFEM: Periodic TxFIFO empty mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in host mode.
Bit 25 HCIM: Host channels interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in host mode.
Bit 24 PRTIM: Host port interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Note: Only accessible in host mode.
Bit 23 Reserved, must be kept at reset value.

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English