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ST STM32F405 User Manual

ST STM32F405
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RM0090 Rev 18 1427/1749
RM0090 USB on-the-go high-speed (OTG_HS)
1543
OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size
register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ)
Address offset: 0x028
Reset value: 0x0000 0200
Host mode:
Peripheral mode:
OTG_HS nonperiodic transmit FIFO/queue status register
(OTG_HS_GNPTXSTS)
Address offset: 0x02C
Reset value: 0x0008 0400
Note: In peripheral mode, this register is not valid.
This read-only register contains the free space information for the nonperiodic TxFIFO and
the nonperiodic transmit request queue.
313029282726252423222120191817161514131211109876543210
NPTXFD NPTXFSA
rw rw
Bits 31:16 NPTXFD: Nonperiodic TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 1024
Bits 15:0 NPTXFSA: Nonperiodic transmit RAM start address
This field contains the memory start address for nonperiodic transmit FIFO RAM.
313029282726252423222120191817161514131211109876543210
TX0FD TX0FSA
r/rw r/rw
Bits 31:16 T0XFD: Endpoint 0 TxFIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 256
Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address
This field contains the memory start address for Endpoint 0 transmit FIFO RAM.
313029282726252423222120191817161514131211109876543210
Reserved
NPTXQTOP NPTQXSAV NPTXFSAV
rr r

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ST STM32F405 Specifications

General IconGeneral
BrandST
ModelSTM32F405
CategoryComputer Hardware
LanguageEnglish

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