ST STM32F405 User Manual

RM0090 Rev 18 1449/1749
RM0090 USB on-the-go high-speed (OTG_HS)
1543
OTG_HS device OUT endpoint common interrupt mask register
(OTG_HS_DOEPMSK)
Address offset: 0x814
Reset value: 0x0000 0000
This register works with each of the Device OUT endpoint interrupt (OTG_HS_DOEPINTx)
registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint
interrupt for a specific status in the OTG_HS_DOEPINTx register can be masked by writing
into the corresponding bit in this register. Status bits are masked by default.
Bit 2 AHBERRM: AHB error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 1 EPDM: Endpoint disabled interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 0 XFRCM: Transfer completed interrupt mask
0: Masked interrupt
1: Unmasked interrupt
313029282726252423222120191817161514131211109876543210
Reserved
NYETMSK
NAKMSK
BERRM
Reserved
OPEM
Reserved
B2BSTUP
STSPHSRXM
OTEPDM
STUPM
AHBERRM
EPDM
XFRCM
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 NYETMSK: NYET interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 13 NAKMSK: NAK interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 12 BERRM: Babble error interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 OPEM: OUT packet error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 Reserved, must be kept at reset value.

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English