ST STM32F405

RM0090 Rev 18 1497/1749
RM0090 USB on-the-go high-speed (OTG_HS)
1543
Reset Error Count
Mask ACK
}
else if (TXERR or BBERR or STALL)
{
Unmask CHH
Disable Channel
if (TXERR)
{
Increment Error Count
Unmask ACK
}
}
else if (CHH)
{
Mask CHH
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
else if (DTERR)
{
Reset Error Count
}
The application is expected to write the requests as and when the Request queue
space is available and until the XFRC interrupt is received.
• Bulk and control IN transactions
A typical bulk or control IN pipelined transaction-level operation is shown in Figure 420.
See channel 2 (ch_2). The assumptions are:
– The application is attempting to receive two maximum-packet-size packets
(transfer size = 1 024 bytes).
– The receive FIFO can contain at least one maximum-packet-size packet and two
status words per packet (72 bytes for FS).
– The nonperiodic request queue depth = 4.