ST STM32F405 User Manual

USB on-the-go high-speed (OTG_HS) RM0090
1514/1749 RM0090 Rev 18
c) The HS_OTG host attempts to send the start split transaction.
d) After successfully transmitting the start split, the OTG_HS host generates the
CHH interrupt.
e) In response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT1 to send the
complete split.
f) After successfully completing the complete split transaction, the OTG_HS host
generates the CHH interrupt.
g) In response to CHH interrupt, de-allocate the channel.
• Interrupt IN split transactions in DMA mode
The sequence of operations in (channel x) is as follows:
a) Initialize and enable channel x for start split as explained in Section : Channel
initialization.
b) The OTG_HS host writes an IN request to the request queue as soon as channel
x receives the grant from the arbiter.
c) The OTG_HS host attempts to send the start split IN token at the beginning of the
next odd micro-frame.
d) The OTG_HS host generates the CHH interrupt after successfully transmitting the
start split IN token.
e) In response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 to send the
complete split.
f) As soon as the packet is received successfully, the OTG_HS host starts writing the
data to the system memory.
g) The OTG_HS host generates the CHH interrupt after transferring the received
data to the system memory.
h) In response to the CHH interrupt, de-allocate or reinitialize the channel for the next
start split.
• Isochronous OUT split transactions in DMA mode
The sequence of operations (channel x) is as follows:
a) Initialize and enable channel x for start split (begin) as explained in Section :
Channel initialization. The application must set the ODDFRM bit in HCCHAR1.
Program the MPS field.
b) The HS_OTG host starts reading the packet.
c) After successfully transmitting the start split (begin), the HS_OTG host generates
the CHH interrupt.
d) In response to the CHH interrupt, reinitialize the registers to send the start split
(end).
e) After successfully transmitting the start split (end), the OTG_HS host generates a
CHH interrupt.
f) In response to the CHH interrupt, de-allocate the channel.
• Isochronous IN split transactions in DMA mode
The sequence of operations (channel x) is as follows:
a) Initialize and enable channel x for start split as explained in Section : Channel
initialization.
b) The OTG_HS host writes an IN request to the request queue as soon as channel
x receives the grant from the arbiter.

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English