Flexible memory controller (FMC) RM0090
1644/1749 RM0090 Rev 18
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write-to-read (and read-to-
write) transaction. This delay allows to match the minimum time between consecutive
transactions (t
EHEL
from NEx high to NEx low) and the maximum time needed by the memory
to free the data bus after a read access (t
EHQZ
). The programmed bus turnaround delay is
inserted between an asynchronous read (muxed or mode D) or write transaction and any
other asynchronous /synchronous read or write to or from a static bank. The bank can be the
same or different in case of read, in case of write the bank can be different except for muxed
or mode D.
In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is
fixed as follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write
transfers to the same static memory bank except for modes muxed and D.
• There is a bus turnaround delay of 1 FMC clock cycle between:
–Two consecutive asynchronous read transfers to the same static memory bank except for
modes muxed and D.
–An asynchronous read to an asynchronous or synchronous write to any static bank or
dynamic bank except for modes muxed and D.
–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.
• There is a bus turnaround delay of 2 FMC clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) access and an asynchronous write or read transfer to
or from static memory bank (the bank can be the same or different for the case of read.
–Two consecutive synchronous reads (burst or single) followed by any
synchronous/asynchronous read or write from/to another static memory bank.
• There is a bus turnaround delay of 3 FMC clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) access and a synchronous read from the same or a
different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset)
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