ST STM32F405 User Manual

Flexible memory controller (FMC) RM0090
1656/1749 RM0090 Rev 18
After WAIT de-assertion, the FMC extends the WAIT phase for 4 HCLK clock cycles.
37.6.8 NAND Flash/PC Card controller registers
PC Card/NAND Flash control registers 2..4 (FMC_PCR2..4)
Address offset: 0x40 + 0x20 * (x – 1), x = 2..4
Reset value: 0x0000 0018
31302928272625242322212019181716151413121110987654321 0
Reserved
ECCPS[2:0]
TAR[3:0]
TCLR[3:0]
Reserved
ECCEN
PWID[1:0]
PTYP
PBKEN
PWAITEN
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 Reserved, must be kept at reset value
Bits 19:17 ECCPS[2:0]: ECC page size.
Defines the page size for the extended ECC:
000: 256 byte
001: 512 byte
010: 1024 byte
011: 2048 byte
100: 4096 byte
101: 8192 byte
Bits 16:13 TAR[3:0]: ALE to RE delay.
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 12:9 TCLR[3:0]: CLE to RE delay.
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value
Bit 6 ECCEN: ECC computation logic enable bit
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Bits 5:4 PWID[1:0]: Data bus width.
Defines the external memory device width.
00: 8 bits
01: 16 bits (default after reset). This value is mandatory for PC Cards.
10: reserved, do not use
11: reserved, do not use

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English