ST STM32F405 User Manual

Revision history RM0090
1724/1749 RM0090 Rev 18
19-Feb-2013
4
(continued)
FSMC:
Updated write FIFO size in Section 36.1: FSMC main features.
Updated Figure 434: FSMC block diagram.
Updated Section 36.5.4: NOR Flash/PSRAM controller asynchronous transactions.
Modified differences between Mode B and mode 1 in Section : Mode 2/B - NOR
Flash.
Modified differences between Mode C and mode 1 in Section : Mode C - NOR
Flash - OE toggling.
Modified differences between Mode D and mode 1 in Section : Mode D -
asynchronous access with extended address.
Updated NWAIT signal in Figure 449: Asynchronous wait during a read access,
Figure 450: Asynchronous wait during a write access, Figure 451: Wait
configurations, Figure 452: Synchronous multiplexed read mode - NOR, PSRAM
(CRAM), and Figure 453: Synchronous multiplexed write mode - PSRAM (CRAM).
Updated Table 195 to Tabl e 214.
Updated Section : SRAM/NOR-Flash chip-select control registers 1..4
(FSMC_BCR1..4).
DEBUG
Updated Figure 485: Block diagram of STM32 MCU and Cortex
®
-M4 with FPU-
level debug support.
Table 315. Document revision history (continued)
Date Version Changes

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English