ST STM32F405

Revision history RM0090
1732/1749 RM0090 Rev 18
14-Oct-2014
8
(continued)
FMC:
Modified step 7 in Section : SDRAM initialization.
Modified SDRAM refresh rate equations and example in Section : SDRAM Refresh
Timer register (FMC_SDRTR) and updated definition of COUNT bits.
Updated EXTMOD definition in Section : SRAM/NOR-Flash chip-select control
registers 1..4 (FMC_BCR1..4).
Updated ADDSET definition in Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FMC_BTR1..4) and Section : SRAM/NOR-Flash write timing
registers 1..4 (FMC_BWTR1..4).
Table 315. Document revision history (continued)
Date Version Changes