ST STM32F405 - Page 1738

Revision history RM0090
1738/1749 RM0090 Rev 18
20-Oct-2015 11
Reset and clock controller (RCC)
Updated STM32F405/407/415/417xx Figure 21: Clock tree.
Updated
General purpuse I/O (GPIOs)
Changed definition of OSPEEDR bits in Section 8.4.3: GPIO port output speed
register (GPIOx_OSPEEDR) (x = A..I/J/K).
LCD-TFT display controller (LTDC):
Changed LRDC_IER into LTDC_IER in Section 16.5: LTDC interrupts.
Updated AHBP[11:0], AAV[11:0 and TOTALW[11:0 in Table 92: LTDC register map
and reset values.
Controller area network (bxCAN):
Updated Section 32.3.4: Acceptance filters and Section 32.7.4: Identifier filtering.
Flexible static memory controller (FSMC)
Updated BUSTURN description in Section : SRAM/NOR-Flash write timing
registers 1..4 (FSMC_BWTR1..4) and Section : SRAM/NOR-Flash chip-select
timing registers 1..4 (FSMC_BTR1..4)
Updated note related to IRS and IFS bits in Section : FIFO status and interrupt
register 2..4 (FSMC_SR2..4).
Flexible memory controller (FMC)
Updated paragraph related to the cacheable read FIFO in Section : SDRAM
controller read cycle.
Updated BUSTURN description in Section : SRAM/NOR-Flash write timing
registers 1..4 (FMC_BWTR1..4) and Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FMC_BTR1..4).
Updated note related to IRS and IFS bits in Section : FIFO status and interrupt
register 2..4 (FMC_SR2..4).
Real-time clock (RTC2)
Updated WUCKSEL prescaler input in Figure 237: RTC block diagram.
Updated 3rd step in Section : Programming the wakeup timer.
Updated WUTWF bit definition in Section 26.6.4: RTC initialization and status
register (RTC_ISR).
Table 315. Document revision history (continued)
Date Version Changes