ST STM32F405

RM0090 Rev 18 341/1749
RM0090 Chrom-Art Accelerator™ controller (DMA2D)
370
Figure 40. DMA2D block diagram
11.3.2 DMA2D control
The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR)
which allows selecting:
The user application can perform the following operations:
• Select the operating mode
• Enable/disable the DMA2D interrupt
• Start/suspend/abort ongoing data transfers
11.3.3 DMA2D foreground and background FIFOs
The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to
be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel
format converter (PFC).
MS30439V1
BG PFC
32
AHB SLAVE
AHB MASTER
256x32-bit
RAM
CLUT itf
256x32-bit
RAM
CLUT itf
ExpanderExpander
32
RGB
A 8
Color mode
X
8-bit A
Amode
A
32
BG
FIFO
FG PFC
32
ExpanderExpander
32 RGB
A 8
Color mode
X
8-bit A
Amode
A
32
FG
FIFO
BLENDER
32
32
A
Red
Green
Blue
32
OUT PFC
Color mode
Converter
32/24/16
OUT
FIFO
Color