ST STM32F405 User Manual

RM0090 Rev 18 49/1749
RM0090 List of figures
56
Figure 98. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Figure 99. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 526
Figure 100. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 527
Figure 101. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Figure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 528
Figure 103. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Figure 104. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 529
Figure 105. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 529
Figure 106. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 531
Figure 107. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 532
Figure 108. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 109. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 110. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 111. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Figure 112. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 536
Figure 113. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 114. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 115. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 116. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 117. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 118. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Figure 119. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 120. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 121. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 545
Figure 122. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 545
Figure 123. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 124. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 125. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Figure 126. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Figure 127. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 554
Figure 128. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 554
Figure 129. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Figure 130. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 131. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Figure 132. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 133. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Figure 134. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Figure 135. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 592
Figure 136. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 592
Figure 137. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 138. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 139. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Figure 140. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Figure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 595
Figure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 595
Figure 143. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Figure 144. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Figure 145. Counter timing diagram, internal clock divided by 4
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. . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Figure 146. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Figure 147. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 599
Figure 149. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English