ST STM32F405 User Manual

Memory and bus architecture RM0090
66/1749 RM0090 Rev 18
0x4001 4800 - 0x4001 4BFF TIM11
APB2
Section 19.5.12: TIM10/11/13/14 register map on
page 694
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
Section 19.4.13: TIM9/12 register map on
page 684
0x4001 3C00 - 0x4001 3FFF EXTI Section 12.3.7: EXTI register map on page 387
0x4001 3800 - 0x4001 3BFF SYSCFG
Section 9.2.8: SYSCFG register maps for
STM32F405xx/07xx and STM32F415xx/17xx on
page 294 and Section 9.3.8: SYSCFG register
maps for STM32F42xxx and STM32F43xxx on
page 301
0x4001 3400 - 0x4001 37FF SPI4 APB2 Section 28.5.10: SPI register map on page 925
0x4001 3000 - 0x4001 33FF SPI1
APB2
Section 28.5.10: SPI register map on page 925
0x4001 2C00 - 0x4001 2FFF SDIO Section 31.9.16: SDIO register map on page 1074
0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 Section 13.13.18: ADC register map on page 430
0x4001 1400 - 0x4001 17FF USART6
Section 30.6.8: USART register map on page 1018
0x4001 1000 - 0x4001 13FF USART1
0x4001 0400 - 0x4001 07FF TIM8
Section 17.4.21: TIM1 and TIM8 register map on
page 587
0x4001 0000 - 0x4001 03FF TIM1
0x4000 7C00 - 0x4000 7FFF UART8
APB1 Section 30.6.8: USART register map on page 1018
0x4000 7800 - 0x4000 7BFF UART7
Table 1. STM32F4xx register boundary addresses (continued)
Boundary address Peripheral Bus Register map

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English