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Real-time clock (RTC) RM0090

822/1749 RM0090 Rev 18

Note: The ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming

them to 0.

This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure

is described in RTC register write protection on page 803.

Bit 5 RSF: Registers synchronization flag

This bit is set by hardware each time the calendar registers are copied into the shadow

registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in

initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow

0: Calendar shadow registers not yet synchronized

1: Calendar shadow registers synchronized

Bit 4 INITS: Initialization status flag

This bit is set by hardware when the calendar year field is different from 0 (backup domain

reset value state).

0: Calendar has not been initialized

1: Calendar has been initialized

Bit 3 SHPF: Shift operation pending

0: No shift operation is pending

1: A shift operation is pending

This flag is set by hardware as soon as a shift operation is initiated by a write to the

RTC_SHIFTR. It is cleared by hardware when the corresponding shift operation has been

executed. Writing to SHPF has no effect.

Bit 2 WUTWF: Wakeup timer write flag

This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in

RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The

wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.

0: Wakeup timer configuration update not allowed

1: Wakeup timer configuration update allowed

Bit 1 ALRBWF: Alarm B write flag

This bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has

been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm B update not allowed

1: Alarm B update allowed.

Bit 0 ALRAWF: Alarm A write flag

This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has

been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm A update not allowed

1: Alarm A update allowed

ST STM32F405 User Manual

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