Real-time clock (RTC) RM0090
830/1749 RM0090 Rev 18
26.6.15 RTC timestamp sub second register (RTC_TSSSR)
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
Note: The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
26.6.16 RTC calibration register (RTC_CALR)
Address offset: 0x3C
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
rrrrrrrrrrrrrrrr
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
rrrr rrrrrrrrrr r r
Bits 31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler’s counter when the timestamp event
occurred.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
rrrrrrrrrrrrrrrr
15141312111098765432 1 0
CALP CALW8 CALW16 Reserved CALM[8:0]
rw rw rw r r r r rw rw rw rw rw rw rw rw rw
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