Index
Index-14 Élan™SC520 Microcontroller User’s Manual
O
OE bit field, 21-7, 21-8
OPMODE_SEL bit field, 10-20, 10-30, 10-31, 10-32
OSC_CTL bit field, 20-7, 20-10
OUT2 bit field, 21-13
P
PAR signal
description, 2-7
Parity Error signal.
See
PERR signal.
PARx register, 4-2
PC/AT compatibility, 1-7
a20 gate support, 6-8
address mapping, 4-12
general-purpose (GP) bus configuration, 13-6
GP-DMA transfers, 14-1, 14-8
interrupt channel mapping (table), 15-12
ISA devices, 13-11
ISA signals and GP bus signals (table), 13-12
normal GP-DMA mode, 14-11
PC/AT peripherals I/O map (table), 4-13
PC/AT port logic, 6-8, 16-4
programmable interrupt controller (PIC)
configuration, 15-18
programmable interval timer (PIT) clock
source, 16-6
real-time clock (RTC), 20-5
Windows compatibility, 4-16
PC/AT port logic
a20 gate support, 6-8
SCP Command Port register (Port 0064h), 6-8
SCP Data Port register (Port 0060h), 6-8
System Control Port A register (Port 0092h), 6-8
System Control Port B register (Port 0061h), 16-4
PCI Address Data Bus signals.
See
AD31–AD0 signals.
PCI Bus Arbiter Status (PCIARBSTA) register
function, 8-2
usage, 8-10, 8-19, 8-23
PCI bus arbitration.
See
system arbitration.
PCI Bus Clock Input signal.
See
CLKPCIIN signal.
PCI Bus Clock Output signal.
See
CLKPCIOUT signal.
PCI bus.
See
PCI host bridge.
PCI Configuration Address (PCICFGADR) register
format (figure), 9-10
function, 9-8
usage, 4-11, 4-12, 9-9, 9-10, 9-17
PCI Configuration Data (PCICFGDATA) register
function, 9-8
usage, 4-11, 9-9, 9-10, 9-11, 9-17
PCI host bridge
arbitration, 8-3
block diagram (figure), 9-2
broken transactions, 8-19
bus arbitration, 8-3
configuration, 9-9
generating configuration cycles, 9-10
configuration space, 4-11
configuring PCI bus devices
network adapter, 3-16
VGA controller on PCI bus, 3-15
host bridge as PCI bus master, 9-11
bus cycles, 9-12
configuration read/write (figure), 9-17
CPU non-posted write cycle (figure), 9-16
CPU posted write cycle (figure), 9-15
CPU read cycle (figure), 9-12
CPU read with external target retry
(figure), 9-14
delayed transaction support, 9-12
read cycles, 9-12
write posting, 9-11
host bridge as PCI bus target, 9-18
address FIFO, 9-20
burst ordering, 9-21
bus cycles, 9-22
external master SDRAM read (figure), 9-24
external master SDRAM write (figure), 9-22
target disconnect (figure), 9-25
command support, 9-19
data coherency, 9-21
delayed transaction support, 9-19
DEVSEL
timing, 9-19
FIFOs and prefetching, 9-20
target address space, 9-18
I/O space, 4-4, 4-12
initialization, 9-29
interrupts, 8-19, 9-27
delayed transaction time-out, 9-27
master abort, 9-27
parity errors, 9-27
retry time-out counter expired, 9-27
system error, 9-27
target abort, 9-27
latency, 9-28
master latency, 9-28
target latency, 9-28
memory space, 4-4, 4-9
operation, 9-8
PCI bus arbiter
bus parking, 8-7
PCI reset, 6-7
registers, 9-7
SDRAM read buffer, 11-12
SDRAM write buffer, 11-12
signal descriptions, 2-6
system design, 9-2
clocking in heavily loaded system (figure), 9-6
clocking in lightly loaded system (figure), 9-6
crystal selection implications, 9-6
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