Index
Index-22 Élan™SC520 Microcontroller User’s Manual
RTCALMMIN register, 20-6
RTCALMSEC register, 20-6
RTCCMOS register, 20-7
RTCCTLA register, 20-7
RTCCTLB register, 20-7
RTCCURDOM register, 20-6
RTCCURDOW register, 20-6
RTCCURHR register, 20-6
RTCCURMIN register, 20-6
RTCCURMON register, 20-6
RTCCURSEC register, 20-6
RTCCURYR register, 20-6
RTCDATA register, 20-6
RTCIDX register, 20-6
RTCMAP register, 15-5
RTCSTAC register, 20-7
RTCSTAD register, 20-7
RTG bit field, 17-3
RTS2
–RTS1 signals
control, 21-4
description, 2-9, 21-6
usage, 21-2
S
S1_GINT_MODE bit field, 15-18
S2 bit field, 15-17, 15-18, 15-19
S2_GINT_MODE bit field, 3-19
S5 bit field, 15-17, 15-18, 15-19
SBIT_ERR bit field, 10-27
SCASA
–SCASB signals
control, 10-10, 10-19, 23-4
description, 2-5
usage, 10-5
SCP Command Port (SCPCMD) register
function, 6-3, 7-1
usage, 6-7, 6-8
SCP Data Port (SCPDATA) register
function, 6-3, 7-1
usage, 6-8
SCPCMD register, 6-3
SCPDATA register, 6-3
SCS3
–SCS0 signals
control, 10-10, 10-19, 23-4
description, 2-5
usage, 10-1, 10-5, 10-12, 10-30
SD_RST_DET bit field, 6-8
SDQM3–SDQM0 signals
control, 10-10, 10-19, 23-4
description, 2-5
usage, 10-6, 10-28, 24-11
SDRAM Address signals.
See
MA12–MA0 signals.
SDRAM Bank 0–3 Ending Address (DRCBENDADR)
register
function, 10-10
usage, 10-32, 10-33, 10-35
SDRAM Bank Configuration (DRCCFG) register
function, 10-10
usage, 10-15, 10-33
SDRAM Buffer Control (DBCTL) register
function, 11-4, 24-2
usage, 11-5, 11-9, 11-13, 24-10
SDRAM Chip Select signals.
See
SCS3–SCS0 signals.
SDRAM Clock Input signal.
See
CLKMEMIN signal.
SDRAM Clock Output signal.
See
CLKMEMOUT signal.
SDRAM Control (DRCCTL) register
function, 10-10, 11-4, 24-2
usage, 10-18, 10-19, 10-30, 24-2, 24-3, 24-7
SDRAM controller
addressing, 10-12
address mapping to MA (table), 10-12
page sizes (table), 10-16
SDRAM devices supported (table), 10-13
supported SDRAM devices, 10-13
block diagram (figure), 10-2
block diagram detail (figure), 10-3
buffering, 10-17
bus cycles, 10-22
auto refresh cycle (figure), 10-27
burst read cycle (figure), 10-22
burst read cycle with ECC enabled
(figure), 10-25
CPU burst write (figure), 10-24
ECC cycles, 10-24
mode register access (figure), 10-27
read-modify-write cycle with ECC (figure), 10-26
write cycle (figure), 10-23
cacheability control, 3-12
code execution control, 3-12
column address configuration (table), 10-15
configuring GP-DMA buffers with PAR
registers, 3-18
control configuration, 10-18
drive-strength selection, 10-19
operation mode select, 10-30
refresh control, 10-18
refresh rates (table), 10-18
write buffer test mode, 10-19
error correction code (ECC), 10-16, 10-27, 10-28
initialization, 10-29
boot process, 10-32
programmable reset, 10-29
SDRAM device initialization, 10-30
auto refresh command, 10-31
load mode register (table), 10-31
mode register programming, 10-31
NOP command, 10-31
operation mode select, 10-20
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