Index
Élan™SC520 Microcontroller User’s Manual Index-23
precharge command, 10-31
sizing algorithm, 10-32
external bank column number, 10-33
internal bank number, 10-34
true external bank ending address, 10-35
interrupts, 10-27
multi-bit error, 10-27
single-bit error, 10-27
latency, 10-28
memory space, 4-4, 4-8
operation, 10-11
registers, 10-10
SDRAM support, 10-11
signal descriptions, 2-5
software considerations, 10-28
disabling buffers during configuration, 10-28
ECC errors, 10-28
write protection, 10-28
system design, 10-1
168-pin SDRAM DIMM configuration
(figure), 10-5
bank configuration (figure), 10-4
clock generation (figure), 10-7
clock generation with external driver
(figure), 10-7
clock loading estimates (table), 10-6
clocking, 10-6
delay calculation, 10-7
estimated capacitance (tables), 10-8
loading, 10-8
pins, 10-5
timing configuration, 10-20
auto-refresh-to-RAS
(T
RC
), 10-21
CAS
latency (C
L
), 10-20
minimum RAS
(T
RAS
), 10-22
RAS
precharge (T
RP
), 10-21
RAS
-to-CAS delay (T
RCD
), 10-21
RAS
-to-RAS, 10-21
write-protection, 3-12, 3-18
SDRAM Memory Write Enable signals.
See
SWEA–
SWEB
signals.
SDRAM Timing Control (DRCTMCTL) register
function, 10-10
usage, 10-20, 10-31, 24-5, 24-9
Serial Data In signals.
See
SIN2–SIN1 signals.
Serial Data Out signals.
See
SOUT2–SOUT1 signals.
Serial Debug Port Data (SDPD) register
format, 25-13
function, 25-2
usage, 25-13
SERR
signal
control, 9-8
description, 2-7
usage, 9-3, 9-27
SET bit field, 20-7
Set Interrupt-Enable Flag (STI)
instruction, 15-7, 15-18, 15-20
SFNM bit field, 15-18
SGL_INT_ENB bit field, 10-27
signal descriptions
AMDebug™ technology, 2-12
configuration, 2-13
descriptions (table), 2-5
general-purpose (GP) bus, 2-7, 2-11
general-purpose (GP) timers, 2-10
GP-DMA controller, 2-7
JTAG, 2-12
PCI host bridge, 2-6
power, 2-14
programmable input/output (PIO), 2-11
programmable interval timer (PIT), 2-10
reset generation, 2-10
ROM/Flash controller, 2-6
SDRAM controller, 2-5
synchronous serial interface (SSI), 2-9
UART serial ports, 2-9
signals
32KXTAL2–32KXTAL1, 2-10
33MXTAL2–33MXTAL1, 2-10
AD31–AD0, 2-6
AMDEBUG_DIS, 2-13
BA1–BA0, 2-5
BBATSEN, 2-14
BOOTCS
,2-6
BR/TC, 2-12
CBE3
–CBE0,2-6
CF_DRAM
,2-12
CF_ROM_GPCS
,2-12
CFG2–CFG0, 2-13
CFG3, 2-13
CLKMEMIN, 2-5
CLKMEMOUT, 2-5
CLKPCIIN, 2-6
CLKPCIOUT, 2-7
CLKTEST, 2-10
CLKTIMER, 2-10
CMDACK, 2-12
CTS2
–CTS1,2-9
DATASTRB, 2-12
DCD2
–DCD1,2-9
DEBUG_ENTER, 2-13
DEVSEL
,2-7
DSR2
–DSR1,2-9
DTR2
–DTR1,2-9
FLASHWR
,2-6
FRAME
,2-7
GND, 2-14
GNT4
–GNT0,2-7
GPA25–GPA0, 2-6, 2-7
GPAEN, 2-8
GPALE, 2-8
GPBHE
,2-8
GPCS7
–GPCS0,2-11
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