GigaDevice Semiconductor GD32F3x0 - Page 11

GD32F3x0 User Manual
11
18.3.12. Smartcard (ISO7816-3) mode ............................................................................................ 459
18.3.13. ModBus communication ..................................................................................................... 461
18.3.14. Receive FIFO ...................................................................................................................... 462
18.3.15. Wakeup from deep-sleep mode .......................................................................................... 462
18.3.16. USART interrupts ................................................................................................................ 463
18.4. Register definition .................................................................................................... 465
18.4.1. Control register 0 (USART_CTL0) ...................................................................................... 465
18.4.2. Control register 1 (USART_CTL1) ...................................................................................... 467
18.4.3. Control register 2 (USART_CTL2) ...................................................................................... 470
18.4.4. Baud rate generator register (USART_BAUD) ................................................................... 472
18.4.5. Prescaler and guard time configuration register (USART_GP) .......................................... 473
18.4.6. Receiver timeout register (USART_RT) ............................................................................. 474
18.4.7. Command register (USART_CMD) .................................................................................... 475
18.4.8. Status register (USART_STAT) .......................................................................................... 475
18.4.9. Interrupt status clear register (USART_INTC) .................................................................... 479
18.4.10. Receive data register (USART_RDATA) ............................................................................ 480
18.4.11. Transmit data register (USART_TDATA) ............................................................................ 481
18.4.12. USART receive FIFO control and status register (USART_RFCS) .................................... 481
19. Inter-integrated circuit interface (I2C) ............................................................. 483
19.1. Overview .................................................................................................................... 483
19.2. Characteristics .......................................................................................................... 483
19.3. Function overview .................................................................................................... 483
19.3.1. SDA and SCL lines ............................................................................................................. 484
19.3.2. Data validation .................................................................................................................... 485
19.3.3. START and STOP signal .................................................................................................... 485
19.3.4. Clock synchronization ......................................................................................................... 485
19.3.5. Arbitration ............................................................................................................................ 486
19.3.6. I2C communication flow ...................................................................................................... 486
19.3.7. Programming model ........................................................................................................... 487
19.3.8. SCL line stretching .............................................................................................................. 496
19.3.9. Use DMA for data transfer .................................................................................................. 497
19.3.10. Packet error checking ......................................................................................................... 497
19.3.11. SMBus support ................................................................................................................... 497
19.3.12. Status, errors and interrupts ............................................................................................... 499
19.4. Register definition .................................................................................................... 501
19.4.1. Control register 0 (I2C_CTL0) ............................................................................................ 501
19.4.2. Control register 1 (I2C_CTL1) ............................................................................................ 503
19.4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 504
19.4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 504
19.4.5. Transfer buffer register (I2C_DATA) ................................................................................... 505
19.4.6. Transfer status register 0 (I2C_STAT0) .............................................................................. 505