GigaDevice Semiconductor GD32F3x0 - Page 12

GD32F3x0 User Manual
12
19.4.7. Transfer status register 1 (I2C_STAT1) .............................................................................. 508
19.4.8. Clock configure register (I2C_CKCFG) .............................................................................. 509
19.4.9. Rise time register (I2C_RT) ................................................................................................ 510
19.4.10. Fast-mode-plus configure register(I2C_FMPCFG)............................................................. 510
20. Serial peripheral interface/Inter-IC sound (SPI/I2S) ....................................... 512
20.1. Overview .................................................................................................................... 512
20.2. Characteristics .......................................................................................................... 512
20.2.1. SPI characteristics .............................................................................................................. 512
20.2.2. I2S characteristics .............................................................................................................. 512
20.3. SPI function overview .............................................................................................. 513
20.3.1. SPI block diagram ............................................................................................................... 513
20.3.2. SPI signal description ......................................................................................................... 513
20.3.3. SPI clock timing and data format ........................................................................................ 514
20.3.4. NSS function ....................................................................................................................... 515
20.3.5. SPI operation modes .......................................................................................................... 516
20.3.6. DMA function....................................................................................................................... 525
20.3.7. CRC function....................................................................................................................... 525
20.3.8. SPI interrupts ...................................................................................................................... 526
20.4. I2S function overview............................................................................................... 527
20.4.1. I2S block diagram ............................................................................................................... 527
20.4.2. I2S signal description .......................................................................................................... 528
20.4.3. I2S audio standards ............................................................................................................ 528
20.4.4. I2S clock ............................................................................................................................. 536
20.4.5. Operation ............................................................................................................................ 537
20.4.6. DMA function....................................................................................................................... 541
20.4.7. I2S interrupts....................................................................................................................... 541
20.5. Register definition .................................................................................................... 543
20.5.1. Control register 0 (SPI_CTL0) ............................................................................................ 543
20.5.2. Control register 1 (SPI_CTL1) ............................................................................................ 545
20.5.3. Status register (SPI_STAT) ................................................................................................. 546
20.5.4. Data register (SPI_DATA) ................................................................................................... 547
20.5.5. CRC polynomial register (SPI_CRCPOLY) ........................................................................ 548
20.5.6. RX CRC register (SPI_RCRC) ........................................................................................... 548
20.5.7. TX CRC register (SPI_TCRC) ............................................................................................ 549
20.5.8. I I2S control register (SPI_I2SCTL) .................................................................................... 550
20.5.9. I2S clock prescaler register (SPI_I2SPSC) ........................................................................ 551
20.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI1 ....................................................... 552
21. HDMI-CEC controller (HDMI-CEC) ................................................................... 554
21.1. Overview .................................................................................................................... 554
21.2. Characteristics .......................................................................................................... 554