RM0090 Rev 18 501/1749
RM0090 LCD-TFT controller (LTDC)
514
16.7.13 LTDC Current Display Status Register (LTDC_CDSR)
This register returns the status of the current display phase which is controlled by the
HSYNC, VSYNC, and Horizontal/Vertical DE signals.
Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set
(active high). If the current display phase is the horizontal synchronization, the HSYNCS bit
is active high.
Address offset: 0x48
Reset value: 0x0000 000F
Note: The returned status does not depend on the configured polarity in the LTDC_GCR register,
instead it returns the current active display phase.
Bits 31:16: CXPOS[15:0]: Current X Position
These bits return the current X position
Bits 15:0 CYPOS[15:0]: Current Y Position
These bits return the current Y position
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
HSYNC
S
VSYNC
S
HDES VDES
rrrr
Bits 31:24 Reserved, must be kept at reset value
Bit 3 HSYNCS: Horizontal Synchronization display Status
0: Active low
1: Active high
Bit 2 VSYNCS: Vertical Synchronization display Status
0: Active low
1: Active high
Bit 1 HDES: Horizontal Data Enable display Status
0: Active low
1: Active high
Bit 0 VDES: Vertical Data Enable display Status
0: Active low
1: Active high
To Next Page
Loading...
Need help?
General
